module ALU (OP, A, B, C, FLAGS);

input A[31:0];
input B[31:0];
input OP[4:0];
output C[31:0];
output FLAGS[2:0];

integer A;
integer B;
wire [4:0] OP;
integer C;
reg [2:0] FLAGS;

//overflow
//b
//sub

always @ (A or B or OP) begin
	FLAGS = 3'b0;
	case (OP)
			0: begin //addl 
				C = A + B;
				if((A<0 == B<0) && (C<0 != A<0)) begin
					FLAGS[0]= 1'b1;
				end
				if(C==0) begin
					FLAGS[1]= 1'b1;
				end
				if(C<0) begin
					FLAGS[2]= 1'b1;
				end
			end				
			1: begin //subl
				C = B - A;
				if((A>0 == B<0) && (C<0 != B<0)) begin
					FLAGS[0]= 1'b1;
				end
				if(C===0) begin
					FLAGS[1]= 1'b1;
				end
				if(C<0) begin
					FLAGS[2]= 1'b1;
				end
			end			   
			2: begin //andl
				C = A & B;
				if(C==0)
					FLAGS[1]= 1'b1;
				if(C<0)
					FLAGS[2]= 1'b1;
			   end
				   
			3: begin //xorl
				C = A ^ B;
				if(C==0)
					FLAGS[1]= 1'b1;
				if(C<0)
					FLAGS[2]= 1'b1;
			   end
				   
			4: begin //incl
				C = B+1;
				if(B>0 && C<0)
					FLAGS[0]= 1'b1;
				if(C==0)
					FLAGS[1]= 1'b1;
				if(C<0)
					FLAGS[2]= 1'b1;
			   end
			5: begin //decl 
				C = B-1;
				if(B<0 && C>0)
					FLAGS[0]= 1'b1;
				if(C==0)
					FLAGS[1]= 1'b1;
				if(C<0)
					FLAGS[2]= 1'b1;
			   end
				
			6: begin //notl
				C = ~B;
				if(C==0)
					FLAGS[1]= 1'b1;
				if(C<0)
					FLAGS[2]= 1'b1;
			   end
			   
			7: begin //orl
				C = A | B;
				if(C==0)
					FLAGS[1]= 1'b1;
				if(C<0)
					FLAGS[2]= 1'b1;
			   end
			   
			8: begin //shll
				C = B << A;
				if (C==0 && B != 0) begin
					FLAGS[0]= 1'b1;
				end
					else
				if (C<0 && B>0) begin
					FLAGS[0]= 1'b1;
				end
					else
				if (C>0 && B<0) begin
					FLAGS[0]= 1'b1;
				end
				if(C==0)
					FLAGS[1]= 1'b1;
				if(C<0)
					FLAGS[2]= 1'b1;
			   end
				   
			9: begin //shrl
				C = B >> A;
				if(C==0)
					FLAGS[1]= 1'b1;
				if(C<0)
					FLAGS[2]= 1'b1;
			 end	
	endcase	
end
	
endmodule
